6502 Assembly

Acorn Tube 1.10 ROM

For my ReCo6502 project, I disassembled Acorn's Tube 1.10 ROM, turned it into an assemblable and changeable source, and put in several (small-ish) bug fixes and other improvements.

Go here for the source, and note the REMs at the top.

First published 5 May 2014.

Acorn BASIC 4r32 ROM

For my ReCo6502 project, I disassembled Acorn's BASIC 4r32 ROM, and turned it into an assemblable and changeable source, producing the exact same binary (regardless of relocation address).

Go here for the source, and note the REMs at the top.

Subsequently, I adapted it to run on a 65816, taking advantage of its new instructions (including 24 bit addressing, used to store up to 16 MB of BASIC variables). That source is ReCo6502 specific, and is not made available here.

First published 5 May 2014.

Verilog HDL

Z65C02 processor core

To maximize the performance of my Soft 6502 Second Processor I developed my own 65C02 core.

Mainly by abusing surplus FPGA block RAM, instruction cycle counts are drastically reduced. The result is a core that needs a ridiculous amount of extra RAM, but roughly doubles the number of instructions per cycle.

There are three slightly different versions. The 'full' one requires roughly 448 KB of (dual-ported) RAM. The 'small' one drops that to 256 KB, but slows down all absolute addressed instructions by one cycle. The 'tiny' one drops that once more to only 64 KB, but slows down JSR and exceptions by one cycle.

Go here for the 'full' source, or here for the 'small' source, or here for the 'tiny' source, and note the comments at the top. For some notes on the development of this core, visit the 6502.org forum here.

First published 14 January 2022.

Signing off

Sources and this text by John Kortink.